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advance information copyright ? intel corporation, 1997 march 1997 order number: 272788-002 83c196ea chmos 16-bit microcontroller automotive the 83c196ea is the first member of a new family of microcontrollers with features that are useful in automotive applications, such as powertrain control. two mbytes of linear address space provide more space for high-level language compilation. a demultiplexed address/data bus and three chip-select signals make it easier to design low-cost memory solutions. the external bus can dynamically switch between multiplexed and demultiplexed operation. note this datasheet contains information on products being sampled or in the initial production phase of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. n 40 mhz operation n optional clock doubler n 2 mbytes of linear address space n 1 kbyte of register ram n 3 kbytes of code ram n 8 kbytes of rom n register-to-register architecture n stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits n 2 peripheral interrupt handlers (pih) provide direct hardware handling of up to 16 peripheral interrupts n peripheral transaction server (pts) with high-speed, microcoded interrupt service routines n up to 83 i/o port pins n 2 full-duplex serial ports with dedicated baud-rate generators n enhanced synchronous serial unit n 8 pulse-width modulator (pwm) outputs with 8-bit resolution n 16-bit watchdog timer n sixteen 10-bit a/d channels with auto- scan mode and dedicated results registers n serial debug unit provides read and write access to code ram with no cpu overhead n chip-select unit (csu) n 3 chip-select pins n dynamic demultiplexed/multiplexed address/data bus for each chip-select n programmable wait states (0, 1, 2, or 3) for each chip-select n programmable bus width (8- or 16-bit) for each chip-select n programmable address range for each chip-select n event processor array (epa) n 4 flexible 16-bit timer/counters n 17 high-speed capture/compare channels n 8 output-only channels capture value of any other timer upon compare, providing easy conversion between angle and time domains n programmable clock output signal n 160-pin qfp package n complete system development support n high-speed chmos technology
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advance information iii contents 83c196ea chmos 16-bit microcontroller 1.0 product overview ................................................................................................................ 1 2.0 nomenclature overview...................................................................................................... 2 3.0 pinout .................................................................................................................................. 3 4.0 signals ................................................................................................................................ 6 5.0 address map ..................................................................................................................... 15 6.0 electrical characteristics................................................................................................... 17 6.1 dc characteristics........................................................................................................ 17 6.2 ac characteristics multiplexed bus mode............................................................... 19 6.3 ac characteristics demultiplexed bus mode .......................................................... 23 6.4 deferred bus timing mode........................................................................................... 27 6.5 ac characteristics serial port, shift register mode................................................ 28 6.6 ac characteristics synchronous serial port ........................................................... 29 6.7 a/d sample and conversion times ............................................................................. 30 6.7.1 ac characteristics a/d converter, 10-bit mode ............................................... 31 6.7.2 ac characteristics a/d converter, 8-bit mode ................................................. 32 6.8 external clock drive ..................................................................................................... 34 6.9 test output waveforms ............................................................................................... 35 7.0 thermal characteristics .................................................................................................... 36 8.0 83c196ea errata .............................................................................................................. 36 9.0 datasheet revision history .............................................................................................. 36 figures 1. 83c196ea block diagram....................................................................................................1 2. product nomenclature .........................................................................................................2 3. 83c196ea 160-pin qfp package .......................................................................................3 4. system bus timing diagram (multiplexed bus mode) ....................................................... 21 5. ready timing diagram (multiplexed bus mode).............................................................. 22 6. system bus timing diagram (demultiplexed bus mode) .................................................. 25 7. ready timing diagram (demultiplexed bus mode) ......................................................... 26 8. deferred bus mode timing diagram.................................................................................. 27 9. serial port waveform shift register mode .................................................................... 28 10. synchronous serial port .................................................................................................... 29 11. external clock drive waveforms........................................................................................ 34 12. ac testing output waveforms........................................................................................... 35 13. float waveforms during 5.0 volt testing........................................................................... 35
iv advance information contents tables 1. description of product nomenclature .................................................................................. 2 2. 83c196ea 160-pin qfp package pin assignments............................................................ 4 3. pin assignment arranged by functional categories............................................................ 5 4. signal descriptions .............................................................................................................. 6 5. 83c196ea address map.................................................................................................... 15 6. dc characteristics at v cc = 4.5 v C 5.5 v.......................................................................... 17 7. ac characteristics, multiplexed bus mode ........................................................................ 19 8. ac timing symbol definitions............................................................................................ 20 9. ac characteristics, demultiplexed bus mode ................................................................... 23 10. serial port timing shift register mode ......................................................................... 28 11. synchronous serial port timing......................................................................................... 29 12. 10-bit a/d operating conditions (1) ................................................................................... 31 13. 10-bit mode a/d characteristics over specified operating conditions (7)........................ 31 14. 8-bit a/d operating conditions (1) ..................................................................................... 32 15. 8-bit mode a/d characteristics over specified operating conditions (7).......................... 33 16. external clock drive........................................................................................................... 34
advance information 1 83c196ea chmos 16-bit microcontroller automotive 1.0 product overview figure 1. 83c196ea block diagram the 83c196ea is highly integrated with an enhanced peripheral set. the serial debug unit (sdu) provides system debug and development capabilities. the sdu can set a single hardware breakpoint and provides read and write access to code ram through a high-speed, dedicated serial link. a stack overflow/underflow monitor assists in code development by causing an unmaskable interrupt if the stack pointer crosses a user- defined boundary. the 16-channel a/d converter supports an auto-scan mode that operates with no cpu code/data ram 3 kbytes eport queue a20:16 source (16) destination (16) ad15:0 sio0 baud-rate generator epa 4 timers ports 7,8 port 11 17 capture/ compares a/d converter bus controller a15:0 serial debug unit watchdog timer stack overflow module pulse-width modulators ssio0 ssio1 rom 8 kbytes a3178-03 sio1 baud-rate generator port 10 bus-control interface unit microcode engine chip-select unit peripheral transaction server memory interface unit register ram 1 kbyte alu interrupt controller peripheral interrupt handler bus control peripheral addr bus (10) peripheral data bus (16) memory addr bus (24) port 12 8 output/ simulcaptures port 9 port 2 memory data bus (16)
2 advance information 83c196ea chmos 16-bit microcontroller automotive overhead. each a/d channel has a dedicated result register. the epa supports high-speed input captures and output compares with 17 programmable, high-speed capture/compare channels. eight output-only channels provide support for time-base conversions by capturing the value of one of four timers when a compare occurs. 2.0 nomenclature overview figure 2. product nomenclature table 1. description of product nomenclature parameter options description temperature and burn-in options a automotive operating temperature range (C40 c to 125 c case) with intel standard burn-in. packaging options s qfp program memory options 3 internal rom process information c chmos product family 196ea device speed no mark 40 mhz program memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-01 process information product family device speed
advance information 3 83c196ea chmos 16-bit microcontroller automotive 3.0 pinout figure 3. 83c196ea 160-pin qfp package a3151-02 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 as83c196ea view of component as mounted on pc board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 ad0 / p3.0 ad1 / p3.1 ad2 / p3.2 ad3 / p3.3 ad4 / p3.4 ad5 / p3.5 ad6 / p3.6 ad7 / p3.7 v cc v cc v ss v ss ad8 / p4.0 ad9 / p4.1 ad10 / p4.2 ad11 / p4.3 ad12 / p4.4 ad13 / p4.5 ad14 / p4.6 ad15 / p4.7 p5.7 / rpd p5.4/breq#/tmode# p5.6 / ready p5.1 / inst p5.0 / ale p5.5 / bhe# / wrh# p5.3 / rd# p5.2 / wr# / wrl# v ss v cc a20 / eport.4 a16 / eport.0 a17 / eport.1 a18 / eport.2 a19 / eport.3 eport.5 / cs0# eport.6 / cs1# eport.7 / cs2# nc nc nc nc nc nc ea# v cc pllen xtal2 xtal1 v ss v cc p2.7 / clkout p2.6 / once# p2.5 p2.4 /rxd1 p2.3 / txd1 p2.2 / extint p2.1 / rxd0 p2.0 / txd0 v cc v ss crbusy# crout crin crdclk v cc nc v ss v ss ach15 ach14 ach13 ach12 ach11 ach10 ach9 ach8 ach7 ach6 nc a15 a14 a13 a12 a11 a10 a9 a8 v cc v ss a7 a6 a5 a4 a3 a2 a1 a0 p9.7 / os7 p9.6 / os6 p9.5 / os5 p9.4 / os4 p9.3 / os3 p9.2 / os2 p9.1 / os1 p9.0 / os0 p7.0 / epa0 / t1clk p7.1 / epa1 / t1rst p7.2 / epa2 / t2clk p7.3 / epa3 / t2rst p7.4 / epa4 / t3clk p7.5 / epa5 / t3rst v ss v cc p7.6 / epa6 / t4clk p7.7 / epa7 / t4rst p8.7 / epa15 p8.6 / epa14 p8.5 / epa13 nc p8.4 / epa12 p8.3 / epa11 p8.2 / epa10 p8.1 / epa9 p8.0 / epa8 p10.5 p10.4 / epa16 p10.3 / sd1 p10.2 / sc1 / chs# p10.1 / sd0 p10.0 / sc0 p11.4 / pwm4 p11.5 / pwm5 p11.6 / pwm6 p11.7 / pwm7 p11.3 / pwm3 p11.2 / pwm2 p11.1 / pwm1 p11.0 / pwm0 v ss v cc p12.4 p12.0 p12.1 p12.2 p12.3 v ss nc v cc nc reset# nmi v ref angnd ach0 ach1 ach2 ach3 ach4 ach5 ? ?? this pin supplies voltage to the phase-locked loop circuitry, so use extra care to keep it stable. this pin supplies voltage to the code ram. maintain at 5 volts to retain data in code ram. nc pins must be unconnected to prevent accidental entry into a test mode. ???
4 advance information 83c196ea chmos 16-bit microcontroller automotive table 2. 83c196ea 160-pin qfp package pin assignments pin name pin name pin name pin name 1 ad0 / p3.0 41 nc 81 ach5 121 nc 2 ad1 / p3.1 42 nc 82 ach4 122 p8.5 / epa13 3 ad2 / p3.2 43 nc 83 ach3 123 p8.6 / epa14 4 ad3 / p3.3 44 nc 84 ach2 124 p8.7 / epa15 5 ad4 / p3.4 45 ea# 85 ach1 125 p7.7 / epa7 / t4rst 6 ad5 / p3.5 46 v cc 86 ach0 126 p7.6 / epa6 / t4clk 7 ad6 / p3.6 47 pllen 87 angnd 127 v cc 8 ad7 / p3.7 48 xtal2 88 v ref 128 v ss 9v cc 49 xtal1 89 nmi 129 p7.5 / epa5 / t3rst 10 v cc 50 v ss 90 reset# 130 p7.4 / epa4 / t3clk 11 v ss 51 v cc 91 nc 131 p7.3 / epa3 / t2rst 12 v ss 52 p2.7 / clkout 92 v cc 132 p7.2 / epa2 / t2clk 13 ad8 / p4.0 53 p2.6 / once# 93 nc 133 p7.1 / epa1 / t1rst 14 ad9 / p4.1 54 p2.5 94 v ss 134 p7.0 / epa0 / t1clk 15 ad10 / p4.2 55 p2.4 / rxd1 95 p12.3 135 p9.0 / os0 16 ad11 / p4.3 56 p2.3 / txd1 96 p12.2 136 p9.1 / os1 17 ad12 / p4.4 57 p2.2 / extint 97 p12.1 137 p9.2 / os2 18 ad13 / p4.5 58 p2.1 / rxd0 98 p12.0 138 p9.3 / os3 19 ad14 / p4.6 59 p2.0 / txd0 99 p12.4 139 p9.4 / os4 20 ad15 / p4.7 60 v cc 100 v cc 140 p9.5 / os5 21 p5.7 / rpd 61 v ss 101 v ss 141 p9.6 / os6 22 p5.4/breq#/tmode# 62 crbusy# 102 p11.0 / pwm0 142 p9.7 / os7 23 p5.6 / ready 63 crout 103 p11.1 / pwm1 143 a0 24 p5.1 / inst 64 crin 104 p11.2 / pwm2 144 a1 25 p5.0 / ale 65 crdclk 105 p11.3 / pwm3 145 a2 26 p5.5 / bhe# / wrh# 66 v cc 106 p11.7 / pwm7 146 a3 27 p5.3 / rd# 67 nc 107 p11.6 / pwm6 147 a4 28 p5.2 / wr# / wrl# 68 v ss 108 p11.5 / pwm5 148 a5 29 v ss 69 v ss 109 p11.4 / pwm4 149 a6 30 v cc 70 ach15 110 p10.0 / sc0 150 a7 31 a20 / eport.4 71 ach14 111 p10.1 / sd0 151 v ss 32 a16 / eport.0 72 ach13 112 p10.2 / sc1 152 v cc 33 a17 / eport.1 73 ach12 113 p10.3 / sd1 153 a8 34 a18 / eport.2 74 ach11 114 p10.4 / epa16 154 a9 35 a19 / eport.3 75 ach10 115 p10.5 155 a10 36 eport.5 / cs0# 76 ach9 116 p8.0 / epa8 156 a11 37 eport.6 / cs1# 77 ach8 117 p8.1 / epa9 157 a12 38 eport.7 / cs2# 78 ach7 118 p8.2 / epa10 158 a13 39 nc 79 ach6 119 p8.3 / epa11 159 a14 40 nc 80 nc 120 p8.4 /epa12 160 a15
advance information 5 83c196ea chmos 16-bit microcontroller automotive table 3. pin assignment arranged by functional categories addr & data input/output input/output (contd) input/output (contd) name pin name pin name pin name pin a0 143 p2.0 / txd0 59 eport.7 38 p12.0 98 a1 144 p2.1 / rxd0 58 p7.0 / epa0 / t1clk 134 p12.1 97 a2 145 p2.2 57 p7.1 / epa1 / t1rst 133 p12.2 96 a3 146 p2.3 / txd1 56 p7.2 / epa2 / t2clk 132 p12.3 95 a4 147 p2.4 / rxd1 55 p7.3 / epa3 / t2rst 131 p12.4 99 a5 148 p2.5 54 p7.4 / epa4 / t3clk 130 a6 149 p2.6 53 p7.5 / epa5 / t3rst 129 analog inputs a7 150 p2.7 52 p7.6 / epa6 / t4clk 126 name pin a8 153 p3.0 1 p7.7 / epa7 / t4rst 125 ach0 86 a9 154 p3.1 2 p8.0 / epa8 116 ach1 85 a10 155 r3.2 3 p8.1 / epa9 117 ach2 84 a11 156 p3.3 4 p8.2 / epa10 118 ach3 83 a12 157 p3.4 5 p8.3 / epa11 119 ach4 82 a13 158 p3.5 6 p8.4 / epa12 120 ach5 81 a14 159 p3.6 7 p8.5 / epa13 122 ach6 79 a15 160 p3.7 8 p8.6 / epa14 123 ach7 78 a16 32 p4.0 13 p8.7 / epa15 124 ach8 77 a17 33 p4.1 14 p9.0 / os0 135 ach9 76 a18 34 p4.2 15 p9.1 / os1 136 ach10 75 a19 35 p4.3 16 p9.2 / os2 137 ach11 74 a20 31 p4.4 17 p9.3 / os3 138 ach12 73 ad0 1 p4.5 18 p9.4 / os4 139 ach13 72 ad1 2 p4.6 19 p9.5 / os5 140 ach14 71 ad2 3 p4.7 20 p9.6 / os6 141 ach15 70 ad3 4 p5.0 25 p9.7 / os7 142 ad4 5 p5.1 24 p10.0 / sc0 110 bus control & status ad5 6 p5.2 28 p10.1 / sd0 111 name pin ad6 7 p5.3 27 p10.2 / sc1 112 ale 25 ad7 8 p5.4 22 p10.3 / sd1 113 bhe#/wrh# 26 ad8 13 p5.5 26 p10.4 / epa16 114 breq# 22 ad9 14 p5.6 23 p10.5 115 cs0# 36 ad10 15 p5.7 21 p11.0 / pwm0 102 cs1# 37 ad11 16 eport.0 32 p11.1 / pwm1 103 cs2# 38 ad12 17 eport.1 33 p11.2 / pwm2 104 inst 24 ad13 18 eport.2 34 p11.3 / pwm3 105 rd# 27 ad14 19 eport.3 35 p11.4 / pwm4 109 ready 23 ad15 20 eport.4 31 p11.5 / pwm5 108 eport.5 36 p11.6 / pwm6 107 eport.6 37 p11.7 / pwm7 106 wr#/wrl# 28
6 advance information 83c196ea chmos 16-bit microcontroller automotive 4.0 signals power & ground processor control name pins name pin angnd 87 clkout 52 v cc 9, 10, 30, 46 ? , 51, 60, 66 ?? , 92, 100, 127, 152 ea# 45 v ss 11, 12, 29, 50, 61, 68, 69, 94, 101, 128, 151 extint 57 v ref 88 nmi 89 once# 53 no connection pllen 47 name pins reset# 90 nc ??? 39C44, 67, 69, 80, 91, 93, 121 rpd 21 tmode# 22 xtal1 49 xtal2 48 ? this pin supplies voltage to the phase-locked loop circuitry, so use extra care to keep it stable. ?? this pin supplies voltage to code ram. to retain data, maintain 5 volts. ??? always leave nc (no connect) pins unconnected to prevent accidental entry into test modes. code debug name pin crbusy# 62 crdclk 65 crin 64 crout 63 table 4. signal descriptions name type description a15:0 i/o system address bus these address lines provide address bits 0C15 during the entire external memory cycle during both multiplexed and demultiplexed bus modes. a20:16 i/o address lines 16C20 these address lines provide address bits 16C20 during the entire external memory cycle, supporting extended addressing of the 2 mbyte address space. note: internally, there are 24 address bits; however, only 21 external address pins (a20:0) are implemented. the internal address space is 16 mbytes (000000Cffffffh) and the external address space is 2 mbytes (00000C1fffffh). the device resets to ff2080h in internal memory or 1f2080h in external memory. a20:16 are multiplexed with eport.4:0. ach15:0 i analog channels these pins are analog inputs to the a/d converter. the angnd and v ref pins must be connected for the a/d converter to function. table 3. pin assignment arranged by functional categories (continued)
advance information 7 83c196ea chmos 16-bit microcontroller automotive ad15:0 i/o address/data lines the function of these pins depend on the bus size and mode. when a bus access is not occurring, these pins revert to their i/o port function. 16-bit multiplexed bus mode : ad15:0 drive address bits 0C15 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 8-bit multiplexed bus mode : ad15:8 drive address bits 8C15 during the entire bus cycle. ad7:0 drive address bits 0C7 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 16-bit demultiplexed mode : ad15:0 drive or receive data during the entire bus cycle. 8-bit demultiplexed mode : ad7:0 drive or receive data during the entire bus cycle. ad15:8 drive the data that is currently on the high byte of the internal bus. ale o address latch enable this active-high output signal is asserted only during external memory cycles. ale signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (a20:16 and ad15:0 for a multiplexed bus; a20:0 for a demultiplexed bus). an external latch can use this signal to demultiplex address bits 0C15 from the address/data bus in multiplexed mode. ale shares a package pin with p5.0. angnd gnd analog ground angnd must be connected for a/d converter operation. angnd and v ss should be nominally at the same potential. bhe# o byte high enable ? during 16-bit bus cycles, this active-low output signal is asserted for word and high-byte reads and writes to external memory. bhe# indicates that valid data is being transferred over the upper half of the system data bus. use bhe#, in conjunction with ad0, to determine which memory byte is being transferred over the system bus: bhe# ad0 byte(s) accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only bhe# shares a package pin with p5.5 and wrh#. ? the chip configuration register 0 (ccr0) determines whether this pin func- tions as bhe# or wrh#. ccr0.2 = 1 selects bhe#; ccr0.2 = 0 selects wrh#. breq# o bus request this active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. you must enable the bus-hold protocol before using this signal. breq# shares a package pin with p5.4. table 4. signal descriptions (continued) name type description
8 advance information 83c196ea chmos 16-bit microcontroller automotive clkout o clock output output of the internal clock generator. the clkout frequency can be programmed to one of five frequencies: the internal operating frequency (f) divided by a factor of two, four, eight, or sixteen, or the same frequency as the oscillator input (f xtal 1 ). clkout has a 50% duty cycle. clkout shares a package pin with p2.7 crbusy# o code ram busy this signal indicates that the serial debug unit (sdu) is not ready to conduct a transaction. crdclk i code ram clock provides the clock signal for the serial debug unit (sdu). the maximum clock frequency equals the operating frequency (f) divided by two. crin i code ram data input serial input for test instructions and data into the serial debug unit (sdu). data is transferred in 8-bit bytes with the most-significant bit (msb) first. each byte is sampled on the rising edge of crdclk. crout o code ram data output serial output for data from the serial debug unit (sdu). data is transferred in 8- bit bytes with the most-significant bit (msb) first. each byte is valid on the rising edge of crdclk. cs2:0# o chip-select lines 0C2 the active-low output cs x # is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x . if the external memory address is outside the range assigned to the three chip selects, no chip-select output is asserted and the bus configuration defaults to the cs2# values. immediately following reset, cs0# is automatically assigned to the range ff2000Cff20ffh (1f2000C1f20ffh if external). cs2:0# share package pins with eport.7:5. ea# i external access this input determines whether memory accesses to special-purpose and program memory partitions (ff2000Cff3fffh) are directed to internal or external memory. these accesses are directed to internal memory if ea# is held high and to external memory if ea# is held low. for an access to any other memory location, the value of ea# is irrelevant. ea# is sampled and latched only on the rising edge of reset#. changing the level of ea# after reset has no effect. on devices with no internal nonvolatile memory, always connect ea# to v ss . epa16:0 i/o event processor array (epa) capture/compare channels high-speed input/output signals for the epa capture/compare channels. epa16:0 share package pins with the following signals: epa0/p7.0/t1clk, epa1/p7.1/t1rst, epa2/p7.2/t2clk, epa3/p7.3/t2rst, epa4/p7.4/t3clk, epa5/p7.5/t3rst, epa6/p7.6/t4clk, epa7/p7.7/t4rst, epa8/p8.0, epa9/p8.1, epa10/p8.2, epa11/p8.3, epa12/p8.4, epa13/p8.5, epa14/p8.6, epa15/p8.7, and epa16/p10.4. table 4. signal descriptions (continued) name type description
advance information 9 83c196ea chmos 16-bit microcontroller automotive eport.7:0 i/o extended addressing port this is a standard 8-bit, bidirectional port. eport.4:0 share package pins with a20:16. eport7:5 share package pins with cs2:0#. extint i external interrupt in normal operating mode, a rising edge on extint sets the extint interrupt pending bit. extint is sampled during phase 2 (clkout high). the minimum high time is one state time. in powerdown mode, asserting the extint signal for at least 50 ns causes the device to resume normal operation. the interrupt need not be enabled, but the pin must be configured as a special-function input. if the extint interrupt is enabled, the cpu executes the interrupt service routine. otherwise, the cpu executes the instruction that immediately follows the command that invoked the power-saving mode. in idle mode, asserting any enabled interrupt causes the device to resume normal operation. extint shares a package pin with p2.2. inst o instruction fetch this active-high output signal is valid only during external memory bus cycles. when high, inst indicates that an instruction is being fetched from external memory. the signal remains high during the entire bus cycle of an external instruction fetch. inst is low for data accesses, including interrupt vector fetches and chip configuration byte reads. inst is low during internal memory fetches. inst shares a package pin with p5.1. nmi i nonmaskable interrupt in normal operating mode, a rising edge on nmi generates a nonmaskable interrupt. nmi has the highest priority of all prioritized interrupts. assert nmi for greater than one state time to guarantee that it is recognized. once# i on-circuit emulation holding once# low during the rising edge of reset# places the device into on-circuit emulation (once) mode. this mode puts all pins into a high- impedance state, thereby isolating the device from other components in the system. the value of once# is latched when the reset# pin goes inactive. while the device is in once mode, you can debug the system using a clip-on emulator. to exit once mode, reset the device by pulling the reset# signal low. to prevent inadvertent entry into once mode, either configure this pin as an output or hold it high during reset and ensure that your system meets the v ih specification. once# shares a package pin with p2.6. os7:0 o event processor array (epa) compare-only channels with simulcapture outputs of the epas compare-only channels. these pins are multiplexed with port 9 and may be configured as standard i/o. os7:0 share package pins with p9.7:0. table 4. signal descriptions (continued) name type description
10 advance information 83c196ea chmos 16-bit microcontroller automotive p2.7:0 i/o port 2 this is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. p2.6 is multiplexed with once#. to prevent inadvertent entry into once mode, either configure this pin as an output or hold it high during reset and ensure that your system meets the v ih specification. port 2 shares package pins with the following signals: p2.0/txd0, p2.1/rxd0, p2.2/extint, p2.3/txd1, p2.4/rxd1, p2.6/once#, and p2.7/clkout. p3.7:0 i/o port 3 this is a memory-mapped, 8-bit, bidirectional port with programmable open- drain or complementary output modes. the pins are shared with the multiplexed address/data bus, which has complementary drivers. p3.7:0 share package pins with ad7:0. p4.7:0 i/o port 4 this is a memory-mapped, 8-bit, bidirectional port with programmable open- drain or complementary output modes. the pins are shared with the multiplexed address/data bus, which has complementary drivers. p4.7:0 share package pins with ad15:8. p5.7:0 i/o port 5 this is a memory-mapped, 8-bit, bidirectional port that is multiplexed with individually selectable control signals. p5.4 is multiplexed with tmode#. if this pin is held low during reset, the device will enter a test mode. to prevent inadvertent entry into a reserved test mode, either configure this pin as an output or hold it high during reset and ensure that your system meets the v ih specification. port 5 shares package pins with the following signals: p5.0/ale, p5.1/inst, p5.2/wr#/wrl#, p5.3/rd#, p5.4/breq#/tmode#, p5.5/bhe#/wrh#, p5.6/ready, and p5.7/rpd. p7.7:0 i/o port 7 this is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. port 7 shares package pins with the following signals: p7.0/epa0/t1clk, p7.1/epa1/t1rst, p7.2/epa2/t2clk, p7.3/epa3/t2rst, p7.4/epa4/t3clk, p7.5/epa5/t3rst, p7.6/epa6/t4clk, and p7.7/epa7/t4rst. p8.7:0 i/o port 8 this is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. p8.7:0 share package pins with epa15:8. p9.7:0 i/o port 9 this is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. p9.7:0 share package pins with os7:0. table 4. signal descriptions (continued) name type description
advance information 11 83c196ea chmos 16-bit microcontroller automotive p10.5:0 i/o port 10 this is a standard, 6-bit, bidirectional port that is multiplexed with individually selectable special-function signals. port 10 shares package pins with the following signals: p10.0/sc0, p10.1/sd0, p10.2/sc1, p10.3/sd1, p10.4/epa16, and p10.5. p11.7:0 i/o port 11 this is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. p11.7:0 share package pins with pwm7:0. p12.4:0 i/o port 12 this is a memory-mapped, 5-bit, bidirectional port. p12.2:0 select the test-rom execution mode. pllen i phase-locked loop enable this active-high input pin enables the on-chip clock doubler. pwm7:0 o pulse width modulator outputs these are pwm output pins with high-current drive capability. pwm7:0 share package pins with p11.7:0. rd# o read read-signal output to external memory. rd# is asserted only during external memory reads. rd# shares a package pin with p5.3. ready i ready input this active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally. when ready is high, cpu operation continues in a normal manner with wait states inserted as programmed in the chip configuration registers or the chip- select x bus control register. ready is ignored for all internal memory accesses. ready shares a package pin with p5.6. reset# i/o reset a level-sensitive reset input to and open-drain system reset output from the microcontroller. either a falling edge on reset# or an internal reset turns on a pull-down transistor connected to the reset# pin for 16 state times. in the powerdown and idle modes, asserting reset# causes the chip to reset and return to normal operating mode. after a device reset, the first instruction fetch is from ff2080h (or 1f2080h in external memory). table 4. signal descriptions (continued) name type description
12 advance information 83c196ea chmos 16-bit microcontroller automotive rpd i return from powerdown timing pin for the return-from-powerdown circuit. if your application uses powerdown mode, connect a capacitor between rpd and v ss if either of the following conditions are true. ? the internal oscillator is the clock source ? the phase-locked loop (pll) circuitry is enabled (see pllen signal description) the capacitor causes a delay that enables the oscillator and pll circuitry to stabilize before the internal cpu and peripheral clocks are enabled. the capacitor is not required if your application uses powerdown mode and if both of the following conditions are true. ? an external clock input is the clock source ? the phase-locked loop circuitry is disabled if your application does not use powerdown mode, leave this pin unconnected. rpd shares a package pin with p5.7. rxd1:0 i/o receive serial data 0 and 1 in modes 1, 2, and 3, rxd0 and 1 receive serial port input data. in mode 0, they functions as either inputs or open-drain outputs for data. rxd0 shares a package pin with p2.1 and rxd1 shares a package pin with p2.4. sc1:0 i/o clock pins for ssio0 and 1 for handshaking mode, configure sc1:0 as open-drain outputs. this pin carries a signal only during receptions and transmissions. when the ssio port is idle, the pin remains either high (with handshaking) or low (without handshaking). sc0 shares a package pin with p10.0, and sc1 shares a package pin with p10.2. sd1:0 i/o data pins for ssio0 and 1 these pins are the data i/o pins for ssio0 and 1. sd0 shares a package pin with p10.1, and sd1 shares a package pin with p10.1. t1clk i timer 1 external clock external clock for timer 1.timer 1 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of t1clk. and external clock for the serial i/o baud-rate generator input (program selectable). t1clk shares a package pin with p7.0 and epa0. t2clk i timer 2 external clock external clock for timer 2. timer 2 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of t2clk. t2clk shares a package pin with p7.2 and epa2. table 4. signal descriptions (continued) name type description
advance information 13 83c196ea chmos 16-bit microcontroller automotive t3clk i timer 3 external clock external clock for timer 3. timer 3 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of t3clk. t3clk shares a package pin with p7.4 and epa4. t4clk i timer 4 external clock external clock for timer 4. timer 2 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of t4clk. t4clk shares a package pin with p7.6 and epa6. t1rst i timer 1 external reset external reset for timer 1. timer 1 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of t1rst. t1rst shares a package pin with p7.1 and epa1. t2rst i timer 2 external reset external reset for timer 2. timer 2 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of t2rst. t2rst shares a package pin with p7.3 and epa3. t3rst i timer 3 external reset external reset for timer 3. timer 3 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of t3rst. t3rst shares a package pin with p7.5 and epa5. t4rst i timer 4 external reset external reset for timer 4. timer 4 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of t4rst. t4rst shares a package pin with p7.6 and epa6. tmode# i test-mode entry if this pin is held low during reset, the device will enter a test mode. the value of several other pins defines the actual test mode. all test modes, except test- rom execution, are reserved for intel factory use. if you choose to configure this signal as an input, always hold it high during reset and ensure that your system meets the v ih specification to prevent inadvertent entry into test mode. tmode# shares a package pin with p5.4 and breq#. txd1:0 o transmit serial data 0 and 1 in serial i/o modes 1, 2, and 3, txd0 and 1 transmit serial port output data. in mode 0, they are the serial clock output. txd0 shares a package pin with p2.0 and txd1 shares a package pin with p2.3. v cc pwr digital supply voltage connect each v cc pin to the digital supply voltage. v ref pwr reference voltage for the a/d converter this pin also supplies operating voltage to the analog portion of the a/d converter. table 4. signal descriptions (continued) name type description
14 advance information 83c196ea chmos 16-bit microcontroller automotive v ss gnd digital circuit ground these pins supply ground for the digital circuitry. connect each v ss pin to ground through the lowest possible impedance path. wr# o write ? this active-low output indicates that an external write is occurring. this signal is asserted only during external memory writes. wr# is multiplexed with p5.2 and wrl#. ? the chip configuration register 0 (ccr0) determines whether this pin func- tions as wr# or wrl#. ccr0.2 = 1 selects wr#; ccr0.2 = 0 selects wrl#. wrh# o write high ? during 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. during 8-bit bus cycles, wrh# is asserted for all write operations. wrh# shares a package pin with p5.5 and bhe#. ? the chip configuration register 0 (ccr0) determines whether this pin func- tions as bhe# or wrh#. ccr0.2 = 1 selects bhe#; ccr0.2 = 0 selects wrh#. wrl# o write low ? during 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. during 8-bit bus cycles, wrl# is asserted for all write operations. wrl# shares a package pin with p5.2 and wr#. ? the chip configuration register 0 (ccr0) determines whether this pin func- tions as wr# or wrl#. ccr0.2 = 1 selects wr#; ccr0.2 = 0 selects wrl#. xtal1 i input crystal/resonator or external clock input input to the on-chip oscillator and the internal clock generators. the internal clock generators provide the peripheral clocks, cpu clock, and clkout signal. when using an external clock sourcel instead of the on-chip oscillator, connect the clock input to xtal1. the external clock signal must meet the v ih specification for xtal1. xtal2 o inverted output for the crystal/resonator output of the on-chip oscillator inverter. leave xtal2 floating when the design uses an external clock source instead of the on-chip oscillator. table 4. signal descriptions (continued) name type description
advance information 15 83c196ea chmos 16-bit microcontroller automotive 5.0 address map table 5. 83c196ea address map hex address description (note 1, note 2) addressing modes ffffff ff4000 external device (memory or i/o) connected to address/data bus indirect, indexed, extended ff3fff ff2400 program memory (note 3) indirect, indexed, extended ff23ff ff2200 program memory (note 3) indirect, indexed, extended ff21ff ff20c0 special-purpose memory (pih vectors; note 3) indirect, indexed, extended ff20bf ff2080 program memory (note 3); (after reset, the first instruction is fetched from ff2080h.) indirect, indexed, extended ff207f ff2000 special-purpose memory (ccbs, interrupt vectors, pts vectors; note 3) indirect, indexed, extended ff1fff ff1000 external device (memory or i/o) connected to address/data bus indirect, indexed, extended ff0fff ff0400 internal code/data ram (identically mapped from page 00h) indirect, indexed, extended ff03ff ff0000 reserved for in-circuit emulators feffff 1f0000 overlaid memory (reserved for future devices); locations x f0000C x f03ffh are reserved for in-circuit emulators indirect, indexed, extended 1effff 004000 external device (memory or i/o) connected to address/data bus indirect, indexed, extended 003fff 002400 a copy of internal rom (ff2400Cff3fffh) if ccb1.2=0 external memory if ccb1.2=1 indirect, indexed, extended 0023ff 002000 external device (memory or i/o) connected to address/data bus indirect, indexed, extended 001fff 001fe0 memory-mapped special-function registers (sfrs) indirect, indexed, extended 001fdf 001c00 peripheral special-function registers (sfrs) indirect, indexed, extended, windowed direct 001bff 001000 external device (memory or i/o) connected to address/data bus indirect, indexed, extended 000fff 000400 internal code/data ram (identically mapped into page ffh) indirect, indexed, extended notes: 1. unless otherwise noted, write 0ffh to reserved memory locations and write 0 to reserved sfr bits. 2. the contents or functions of reserved locations may change in future device revisions, in which case a program that relies on one or more of these locations might not function properly. 3. external memory if ea# is low; internal rom if ea# is high.
16 advance information 83c196ea chmos 16-bit microcontroller automotive 0003ff 000100 upper register file (general-purpose register ram) indirect, indexed, windowed direct 0000ff 00001a lower register file (general-purpose register ram) direct, indirect, indexed 000019 000000 lower register file (stack pointer and cpu sfrs) direct, indirect, indexed table 5. 83c196ea address map (continued) hex address description (note 1, note 2) addressing modes notes: 1. unless otherwise noted, write 0ffh to reserved memory locations and write 0 to reserved sfr bits. 2. the contents or functions of reserved locations may change in future device revisions, in which case a program that relies on one or more of these locations might not function properly. 3. external memory if ea# is low; internal rom if ea# is high.
advance information 17 83c196ea chmos 16-bit microcontroller automotive 6.0 electrical characteristics 6.1 dc characteristics absolute maximum ratings ? storage temperature .................................. C60c to +150c supply voltage with respect to v ss ............... C0.5 v to +7.0 v power dissipation .......................................................... 1.5 w operating conditions ? t c (case temperature under bias) .............. C40c to +125c v cc (digital supply voltage) .............................. 4.5 v to 5.5 v v ref (analog supply voltage) ........................... 4.5 v to 5.5 v f xtal 1 (input frequency for v cc = 4.5 v C 5.5 v) (note 1) ................................................ 20 mhz to 40 mhz note: 1. this device is static and should operate below 1 hz, but has been tested only down to 20 mhz. notice : this document contains information on products in the design phase of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. ? warning : stressing the device beyond the absolute maximum ratings may cause perma- nent damage. these are stress ratings only. oper- ation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 6. dc characteristics at v cc = 4.5 v C 5.5 v symbol parameter min typical (note 1) max units test conditions i cc v cc supply current 120 135 ma xtal1 = 40 mhz v cc = 5.5 v device in reset i idle idle mode current 60 95 ma xtal1 = 40 mhz v cc = 5.5 v i pd powerdown mode current 20 50 a v cc = 5.5 v i ref a/d reference supply current tbd ma xtal1 = 40 mhz v cc = v ref = 5.5 v device in reset i injd maximum injection current per port on bidirectional pins (note 4) C10 10 ma i li input leakage current (standard inputs except analog inputs) C10 10 a v ss < v in < v cc notes: 1. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature with v cc = 5.0 v. 2. for p2.7:0, p3.7:0, p4.7:0, p5.7:0, p6.7:0, p10.3:0, p11.7:0, p12.4:0, ad15:0, ea#, reset#, pllen, nmi, tdi, tclk, once#, and xtal1. 3. for p7.7:0, p8.7:0, p9.7:0, and p10.5:4. 4. the maximum injection current is not tested. the device is designed to meet this specification. 5. pin capacitance is not tested. this value is based on design simulations.
18 advance information 83c196ea chmos 16-bit microcontroller automotive i li 1 input leakage current (analog inputs) C300 300 na v ss + 100 mv < v in < v ref C 100 mv i ih input high current (nmi only) 175 a nmi = v cc = 5.5v v il 1 input low voltage (note 2) C0.5 0.3 v cc v v ih 1 input high voltage (note 2) 0.7 v cc v cc + 0.5 v v il 2 input low voltage (note 3) C0.5 0.4 v cc v v ih 2 input high voltage (note 3) 0.7 v cc v cc + 0.5 v v ol 1 output low voltage (output configured as complementary) 0.3 0.45 1.5 v v v i ol = 200 a i ol = 3.2 ma i ol = 7.0 ma v oh 1 output high voltage (output configured as complementary) v cc C 0.3 v cc C 0.7 v cc C 1.5 v v v i oh = C200 a i oh = C3.2 ma i oh = C7.0 ma v ol 2 output low voltage in reset 0.5 v i ol = 15 a i oh 2 output high current in reset C30 C75 C90 C120 C240 C280 ma ma ma v oh 2 = v cc C 1.0v v oh 2 = v cc C 2.5v v oh 2 = v cc C 4.0v i oh 3 output high current in reset on port 12 tbd tbd tbd C50 C110 C130 ma ma ma v oh 3 = v cc C 1.0v v oh 3 = v cc C 2.5v v oh 3 = v cc C 4.0v v oh 2 output high voltage in reset v cc C 1 v i oh = C15 a v hys hysteresis voltage on all inputs except xtal1 700 mv c s pin capacitance (any pin to v ss ) (note 5) 10 pf r rst pull-up resistor on reset# pin 995k w v cc = 5.5 v, v in = 4.0 v table 6. dc characteristics at v cc = 4.5 v C 5.5 v (continued) symbol parameter min typical (note 1) max units test conditions notes: 1. typical values are based on a limited number of samples and are not guaranteed. the values listed are at room temperature with v cc = 5.0 v. 2. for p2.7:0, p3.7:0, p4.7:0, p5.7:0, p6.7:0, p10.3:0, p11.7:0, p12.4:0, ad15:0, ea#, reset#, pllen, nmi, tdi, tclk, once#, and xtal1. 3. for p7.7:0, p8.7:0, p9.7:0, and p10.5:4. 4. the maximum injection current is not tested. the device is designed to meet this specification. 5. pin capacitance is not tested. this value is based on design simulations.
advance information 19 83c196ea chmos 16-bit microcontroller automotive 6.2 ac characteristics multiplexed bus mode test conditions: capacitive load on all pins = 50 pf, rise and fall times = 3 ns. table 7. ac characteristics, multiplexed bus mode symbol parameter min max units f xtal 1 frequency on xtal1, pll in 1x mode 16 40 mhz (1, 8) frequency on xtal1, pll in 2x mode 8 20 mhz (8) f operating frequency, f = f xtal 1 ; pll in 1x mode 16 40 mhz (8) operating frequency, f = 2f xtal 1 ; pll in 2x mode t period, t = 1/f 25 62.5 ns t avdv address valid to input data valid 3t C 40 ns (2) t rldv rd# low to input data valid t C 18 ns (2) t chdv clkout high to input data valid 2t C 35 ns (9) t rhdz rd# high to input data float t + 5 ns t rxdx data hold after rd# inactive 0 ns t xhch xtal1 rising edge to clkout high or low 3 50 ns (9) t clcl clkout cycle time 2t ns (9) t chcl clkout high period t C 10 t + 10 ns (9) t cllh clkout falling to ale rising C 10 10 ns (9) t llch ale falling to clkout rising C 10 10 ns (9) t lhlh ale cycle time 4t ns (2) t lhll ale high period t C 10 t + 10 ns t avll address setup to ale low t C 15 ns t llax address hold after ale low t C 15 ns t llrl ale low to rd# low t C 15 ns t rlcl rd# low to clkout low C 10 10 ns (9) t rlrh rd# low to rd# high t C 10 ns (2) t rhlh rd# high to ale rising t C 5 t + 15 ns (3) notes: 1. 16 mhz is the maximum input frequency when using an external crystal oscillator; however, 40mhz can be applied with an external clock source. 2. if wait states are used, add 2t n , where n = number of wait states. 3. assuming back-to-back bus cycles. 4. when forcing wait states using the buscon register, add 2t n. 5. exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. the first falling edge of ready is not synchronized to a clkout edge; therefore, one programmed wait state is required. 8. device is static by design but has been tested only down to 20 mhz. 9. assumes clkout is operating in divide-by-two mode (f/2).
20 advance information 83c196ea chmos 16-bit microcontroller automotive t rlaz rd# low to address float 5 ns t llwl ale low to wr# low t C 12 ns t qvwh data stable to wr# rising edge t C 14 ns ( 2 ) t chwh clkout high to wr# rising edge C 10 5 ns (9) t wlwh wr# low to wr# high t C 10 ns (2) t whqx data hold after wr# high t C 15 ns t whlh wr# high to ale high t C 15 t + 10 ns t whbx bhe#, inst hold after wr# high t C 4 ns t whax ad15:8, cs x # hold after wr# high t C 4 ns (6) t rhbx bhe#, inst hold after rd# high t C 5 ns t rhax ad15:8, cs x # hold after rd# high t C 5 ns (6) t w hsh a20:0, cs x # hold after wr# high 0 ns t rhsh a20:0, cs x # hold after rd# high 0 ns t avyv ad15:0 valid to ready setup 2t C 40 ns (4) t clyx ready hold after clkout low 0 2t C 40 ns (5, 7, 9) t ylyh non-ready time no upper limit ns table 8. ac timing symbol definitions signals conditions a ? address l ale w wr#, wrh#, wrl# h high b bhe# q output data x xtal1 l low c clkout r rd# y ready v valid d input data s cs x # x no longer valid z floating ? address bus (demultiplexed mode) or address/data bus (multiplexed mode) table 7. ac characteristics, multiplexed bus mode (continued) symbol parameter min max units notes: 1. 16 mhz is the maximum input frequency when using an external crystal oscillator; however, 40mhz can be applied with an external clock source. 2. if wait states are used, add 2t n , where n = number of wait states. 3. assuming back-to-back bus cycles. 4. when forcing wait states using the buscon register, add 2t n. 5. exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. the first falling edge of ready is not synchronized to a clkout edge; therefore, one programmed wait state is required. 8. device is static by design but has been tested only down to 20 mhz. 9. assumes clkout is operating in divide-by-two mode (f/2).
advance information 21 83c196ea chmos 16-bit microcontroller automotive figure 4. system bus timing diagram (multiplexed bus mode) clkout ale rd# a3252-01 ad15:0 (read) wr# ad15:0 (write) bhe#, inst ad15:8 a20:16 t lhlh address out extended address out t t cllh t clcl t chdv t rlcl t chcl t llch t llrl t rhlh t rlrh t rldv t rhdz data in t rlaz t llax address out t avdv t avll t chwh t whlh t llwl t wlwh t whqx data out address out t wlwh t qvwh t whbx , t rhbx high address out t whsh , t rhsh cs x # t whax , t rhax t lhll
22 advance information 83c196ea chmos 16-bit microcontroller automotive figure 5. ready timing diagram (multiplexed bus mode) clkout ready ale a3249-01 t clyx (min) t lhlh + 2t t avdv + 2t rd# ad15:0 (read) ad15:0 (write) bhe#, inst a20:16 cs x # t rlrh + 2t t avyv data out extended address out address out t clyx (max) data in address out t rldv + 2t t wlwh + 2t t qvwh + 2t wr#
advance information 23 83c196ea chmos 16-bit microcontroller automotive 6.3 ac characteristics demultiplexed bus mode test conditions: capacitive load on all pins = 50 pf, rise and fall times = 3 ns. table 9. ac characteristics, demultiplexed bus mode symbol parameter min max units f xtal 1 frequency on xtal1, pll in 1x mode 16 40 mhz (1,8) frequency on xtal1, pll in 2x mode 8 20 mhz (8) f operating frequency, f = f xtal 1 ; pll in 1x mode 16 40 mhz operating frequency, f = 2f xtal 1 ; pll in 2x mode t period, t = 1/f 25 62.5 ns t avdv address valid to input data valid 4t C 23 ns (2) t rldv rd# low to input data valid 3t C 25 ns (2) t avwl address valid to wr# low t ns t avrl address valid to rd# low t C 8 ns t sldv chip select low to data valid 4t C 27 ns (2) t chdv clkout rising edge to input data valid 2t C 25 ns (9) t rhdz rd# high to input data float t - 5 ns t rhrl read high to next read low t C 5 ns t rxdx data hold after rd# inactive 0 ns t xhch xtal1 high to clkout high or low 10 35 ns (9) t clcl clkout cycle time 2t ns (9) t chcl clkout high period t C 5 t + 5 ns (9) t cllh clkout falling ale rising C 5 5 ns (9) t rlcl rd# low to clkout low C 5 5 ns (9) t rlrh rd# low to rd# high 3t C 10 ns (2) t rhlh rd# rising to ale rising t C 4 t + 12 ns ( 3 ) t wlcl wr# low to clkout falling C 12 5 ns (9) t qvwh data stable to wr# rising edge 3t C 18 ns (3) 1. 16 mhz is the maximum input frequency when using an external crystal oscillator; however, 40 mhz can be applied with an external clock source. 2. if wait states are used, add 2t n , where n = number of wait states. 3. assuming back-to-back bus cycles. 4. when forcing wait states using the buscon register, add 2t n. 5. exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. the first falling edge of ready is not synchronized to a clkout edge; therefore, one programmed wait state is required. 8. device is static by design but has been tested only down to 20 mhz. 9. assumes clkout is operating in divide-by-two mode (f/2).
24 advance information 83c196ea chmos 16-bit microcontroller automotive t chwh clkout high to wr# rising edge C 5 10 ns (9) t wlwh wr# low to wr# high 3t C 12 ns (2) t whqx data hold after wr# rising edge t t + 15 ns t whbx bhe#, inst hold after wr# high t ns t whax a20:0, cs x # hold after wr# high 0 ns t rhbx bhe#, inst hold after rd# high t ns t rhax a20:0, cs x # hold after rd# high 0 ns t avyv a20:0 valid to ready setup 3t C 23 ns (4) t clyx ready hold after clkout low 0 2t C 28 ns (5, 7,9) t ylyh non ready time no upper limit ns table 9. ac characteristics, demultiplexed bus mode (continued) symbol parameter min max units 1. 16 mhz is the maximum input frequency when using an external crystal oscillator; however, 40 mhz can be applied with an external clock source. 2. if wait states are used, add 2t n , where n = number of wait states. 3. assuming back-to-back bus cycles. 4. when forcing wait states using the buscon register, add 2t n. 5. exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. the first falling edge of ready is not synchronized to a clkout edge; therefore, one programmed wait state is required. 8. device is static by design but has been tested only down to 20 mhz. 9. assumes clkout is operating in divide-by-two mode (f/2).
advance information 25 83c196ea chmos 16-bit microcontroller automotive figure 6. system bus timing diagram (demultiplexed bus mode) clkout ale rd# a5397-01 ad15:0 (read) wr# ad15:0 (write) bhe#, inst a20:0 address out t chcl t clcl t chwh t rhrl t rhdz data in t rlrh t avdv t whqx t whax t wlcl data out t wlwh t qvwh t whbx , t rhbx cs x # t cllh t t rhlh t avrl t rhax t sldv t chdv t rldv t avwl
26 advance information 83c196ea chmos 16-bit microcontroller automotive figure 7. ready timing diagram (demultiplexed bus mode) clkout ready ale a5398-01 t chyx (min) t lhlh + 2t t avdv + 2t rd# ad15:0 (read) ad15:0 (write) bhe#, inst a20:16 cs x # t rlrh + 2t t avyv data out extended address out t chyx (max) data in t rldv + 2t t wlwh + 2t t qvwh + 2t wr#
advance information 27 83c196ea chmos 16-bit microcontroller automotive 6.4 deferred bus timing mode deferred bus cycle mode: this bus mode (enabled by setting ccb1.5) reduces bus contention when using the 83c196ea in demultiplexed mode with slow memories. as shown in figure 8, a delay of 2t occurs in the first bus cycle following a chip-select output change and the first write cycle following a read cycle . figure 8. deferred bus mode timing diagram clkout ale rd# a3246-02 t whlh + 2t t rhlh + 2t t avrl + 2t t avwl + 2t ad15:0 (read) wr# ad15:0 (write) bhe#, inst a20:0 cs x # t avdv + 2t t lhlh + 2t data in data in data out valid valid data out address out data out
28 advance information 83c196ea chmos 16-bit microcontroller automotive 6.5 ac characteristics serial port, shift register mode figure 9. serial port waveform shift register mode table 10. serial port timing shift register mode symbol parameter min max units t xlxl serial port clock period sp_baud 3 x 002h sp_baud = x 001h ? 6t 4t ns ns t xlxh serial port clock falling edge to rising edge sp_baud 3 x 002h sp_baud = x 001h ? 4t C 27 2t C 27 4t + 27 2t + 27 ns ns t qvxh output data setup to clock high 4t C 30 ns t xhqx output data hold after clock high 2t C 30 ns t xhqv next output data valid after clock high 2t + 30 ns t dvxh input data setup to clock high 2t + 30 ns t xhdx input data hold after clock high 0 ns t xhqz last clock high to output float t + 30 ns ? the minimum baud-rate (sp_baud) register value for receive is x 002h and the minimum baud-rate (sp_baud) register value for transmit is x 001h. a2080-03 valid valid valid valid valid valid valid valid rxd x (in) txd x 01 2 3 4 5 6 7 t qvxh t xlxl t dvxh t xhqv t xhqz t xhdx t xhqx t xlxh rxd x (out)
advance information 29 83c196ea chmos 16-bit microcontroller automotive 6.6 ac characteristics synchronous serial port figure 10. synchronous serial port table 11. synchronous serial port timing symbol parameter min max units t clcl synchronous serial port clock period 8t ns t clch synchronous serial port clock falling edge to rising edge 4t ns t d 1 vd setup time for msb output tbd ns t cxdv setup time for d6:0 output 3t + 20 ns t cxdx output data hold after clock low t 3t + 20 ns t dvcx setup time for input data 10 ns t dxcx input data hold after clock high t + 5 ns msb d6 d5 d4 d3 d2 d1 d0 valid valid valid valid valid valid valid valid 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 sc x (normal transfers) sd x (out) sd x (in) sc x (handshaking transfers) slave receiver pulls sc x low a3233-02 t chch t chcl t clch ste bit t d1dv t cxdx t cxdv t dvcx t dxcx assumes that the ssio is configured to sample incoming data on the rising clock edge and sample outgoing data on the falling clock edge, and that the ssio is configured to pull the clock signal low while the channel is idle. ? ?
30 advance information 83c196ea chmos 16-bit microcontroller automotive 6.7 a/d sample and conversion times two parameters, sample time and conversion time, control the time required for an a/d conversion. the sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. if this time is too short, the sample capacitor will not charge completely. if the sample time is too long, the input voltage may change and cause conversion errors. the conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. the conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. excessively long conversion times allow the sample capacitor to discharge, degrading accuracy. the ad_time register programs the a/d sample and conversion times. use the t sam and t conv specifica- tions in tables 12 and 14 to determine appropriate values for sam and conv; otherwise, erroneous conversion results may occur. when the sam and conv values are known, write them to the ad_time register. do not write to this register while a conversion is in progress; the results are unpredictable. use the following formulas to determine the sam and conv values. where: sam equals a number, 1 to 7 conv equals a number, 2 to 31 t sam is the sample time, in m sec (tables 12 and 14) t conv is the conversion time, in m sec (tables 12 and 14) f is the operating frequency, in mhz b is the number of bits to be converted (8 or 10) at 40 mhz, to meet t sam and t conv minimum specifications: 10-bit mode: 8-bit mode: sam t sam f2 C 8 ------------------------------ - = conv t conv f 3 C 2b ---------------------------------- 1 C = sam 567 ,, [] =t sam 1 m s 3 t conv 18 19 20 ? 31 ,,,, [] =t conv 10 m s 3 t sam 567 ,, [] =t sam 1 m s 3 t conv 23 24 ? 31 ,,, [] =t conv 10 m s 3 t
advance information 31 83c196ea chmos 16-bit microcontroller automotive 6.7.1 ac characteristics a/d converter, 10-bit mode table 12. 10-bit a/d operating conditions (1) symbol description min max units notes t c case temperature C 40 + 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v 2 t sam sample time 1.0 m s3 t conv conversion time 10.0 15.0 m s3 notes: 1. angnd and v ss should nominally be at the same potential. 2. v ref must not exceed v cc by more than + 0.5 v because v ref supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. program the ad_time register to meet the t sam and t conv specifications. table 13. 10-bit mode a/d characteristics over specified operating conditions (7) parameter typical (2) min max units (1) notes resolution 1024 10 1024 10 levels bits absolute error 0 3.0 lsbs full-scale error 0.25 0.5 lsbs zero offset error 0.25 0.5 lsbs nonlinearity 1.0 2.0 3.0 lsbs differential nonlinearity C 0.75 + 0.75 lsbs channel-to-channel matching 0.1 0 1.0 lsbs repeatability 0.25 0 lsbs temperature coefficients: offset full-scale differential nonlinearity 0.009 0.009 0.009 lsb/c lsb/c lsb/c off-isolation C 60 db 2, 3, 4 notes: 1. an lsb , as used here, has a value of approximately 5 mv. 2. most parts will need these values at 25 c, but they are not tested or guaranteed. 3. dc to 100 khz. 4. multiplexer break-before-make guaranteed. 5. resistance from device pin, through internal multiplexer, to sample capacitor. 6. applying voltage beyond these specifications will degrade the accuracy of other channels being con- verted. 7. all conversions were performed with processor in idle mode. 8. 100 mv < v in < v ref C 100 mv.
32 advance information 83c196ea chmos 16-bit microcontroller automotive 6.7.2 ac characteristics a/d converter, 8-bit mode feedthrough C 60 db 2, 3 v cc power supply rejection C 60 db 2, 3 input series resistance 750 1.2k w 5 voltage on analog input pin angnd v ref v 6 sampling capacitor 3.0 pf dc input leakage 100 0 300 na 8 table 14. 8-bit a/d operating conditions (1) symbol description min max units note s t c case temperature C 40 + 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v 2 t sam sample time 1.0 m s3 t conv conversion time 8.0 15.0 m s3 notes: 1. angnd and v ss should nominally be at the same potential. 2. v ref must not exceed v cc by more than + 0.5 v because v ref supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. program the ad_time register to meet the t sam and t conv specifications. table 13. 10-bit mode a/d characteristics over specified operating conditions (7) (continued) parameter typical (2) min max units (1) notes notes: 1. an lsb , as used here, has a value of approximately 5 mv. 2. most parts will need these values at 25 c, but they are not tested or guaranteed. 3. dc to 100 khz. 4. multiplexer break-before-make guaranteed. 5. resistance from device pin, through internal multiplexer, to sample capacitor. 6. applying voltage beyond these specifications will degrade the accuracy of other channels being con- verted. 7. all conversions were performed with processor in idle mode. 8. 100 mv < v in < v ref C 100 mv.
advance information 33 83c196ea chmos 16-bit microcontroller automotive table 15. 8-bit mode a/d characteristics over specified operating conditions (7) parameter typical (2) min max units (1) notes resolution 256 8 256 8 levels bits absolute error 0 1.0 lsbs full-scale error 0.5 lsbs zero offset error 0.5 lsbs nonlinearity 0 1.0 lsbs differential nonlinearity C 0.5 + 0.5 lsbs channel-to-channel matching 0 1.0 lsbs repeatability 0.25 0 lsbs temperature coefficients: offset full-scale differential nonlinearity 0.003 0.003 0.003 lsb/ c lsb/ c lsb/ c off isolation C 60 db 2, 3, 4 feedthrough C 60 db 2, 3 v cc power supply rejection C 60 db 2, 3 input series resistance 750 1.2k w 5 voltage on analog input pin angnd v ref v6 sampling capacitor 3.0 pf dc input leakage 100 0 300 na 8 notes: 1. an lsb , as used here, has a value of approximately 20 mv. 2. most parts will need these values at 25 c, but they are not tested or guaranteed. 3. dc to 100 khz. 4. multiplexer break-before-make guaranteed. 5. resistance from device pin, through internal multiplexer, to sample capacitor. 6. applying voltage beyond these specifications will degrade the accuracy of other channels being con- verted. 7. all conversions were performed with processor in idle mode. 8. 100 mv < v in < v ref C 100 mv.
34 advance information 83c196ea chmos 16-bit microcontroller automotive 6.8 external clock drive figure 11. external clock drive waveforms table 16. external clock drive symbol parameter min max units 1/t xlxl oscillator frequency (f xtal 1 ) 8 40 (1) mhz (2) t xlxl oscillator period (t xtal 1 ) 50 125 ns t xhxx high time 0.35t xtal 1 0.65t xtal 1 ns t xlxx low time 0.35t xtal 1 0.65t xtal 1 ns t xlxh rise time 10 ns t xhxl fall time 10 ns note: 1. 16 mhz is the maximum input frequency when using an external crystal oscillator; however, 32 mhz can be applied with an external clock source. 2. these values represent pll-bypass mode. t xlxx a2119-03 t xhxx t xhxl t xlxl 0.3 v cc C 0.5 v 0.7 v cc + 0.5 v t xlxh 0.7 v cc + 0.5 v 0.3 v cc C 0.5 v xtal1
advance information 35 83c196ea chmos 16-bit microcontroller automotive 6.9 test output waveforms figure 12. ac testing output waveforms figure 13. float waveforms during 5.0 volt testing test points 2.0 v 0.8 v note: ac testing inputs are driven at 3.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 2.0 v for a logic 1 and 0.8 v for a logic 0. 3.5 v 0.45 v a2120-04 2.0 v 0.8 v v load v load C 0.15 v v load + 0.15 v timing reference points v oh C 0.15 v v ol + 0.15 v note: for timing purposes, a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs with i ol /i oh 15 ma. a2121-03
36 advance information 83c196ea chmos 16-bit microcontroller automotive 7.0 thermal characteristics all thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. values will change depending on operating conditions and the application. the intel packaging handbook (order number 240800) describes intels thermal impedance test methodology. the components quality and reliability handbook (order number 210997) provides quality and reliability information. 8.0 83c196ea errata the 83c196ea may contain design defects or errors known as errata. characterized errata that may cause the 83c196eas behavior to deviate from published specifications are documented in a specification update. specification updates can be obtained from your local intel sales office or from the world wide web ( www.intel.com ). 9.0 datasheet revision history this datasheet is valid for devices with an c at the end of the topside field process order (fpo) number. datasheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. this is the -002 version of the datasheet. the following changes were made in this version: 1. the status of the datasheet was revised from product preview to advance information. 2. the frequency designation was changed from 32 mhz to 40 mhz. 3. the following dc characteristics specifications were either changed or added: ?i cc (max) ?i idle (max) ?i oh 2 ?i oh 3 4. the following ac characteristics multiplexed bus mode specifications were changed: ?t chcl (max) ?t llch (min/max) ?t rlcl (max) ?t chwh (min) ?t whlh (max) ?t avyv (max) ?t clyx (max) ?t whqx (min) ?t llax (min) ?t rldv (max) 5. the following ac characteristics demulti- plexed bus mode specifications were changed: ?t avdv (max) ?t rldv (max) ?t sldv (max) ?t chdv (max) ?t xhch min/(max) ?t chcl (min/max) ?t cllh (min/max) ?t rlcl (min) ?t rlrh (min) ?t rhlh (max) ?t wlcl (min) ?t qvwh (min) ?t chwh (min) ?t wlwh (min) ?t whqx (max) ?t whbx (min) ?t rhbx (min) ?t avyv (max) ?t clyx (max) 6. the following ac characteristics demulti- plexed bus mode specifications were removed: ?t llch ?t lhlh ?t lhll ?t whlh 7. address out line in the system bus timing diagram (demultiplexed bus mode) was cor- rected from a20:16 to a20:0. 8. t chyx (max) timing was corrected in the ready timing diagram to show the rising edge of ready after the falling edge of clkout. 9. hold#/hlda# timings section was removed, and all references to either hold# or hlda# were removed. 10. synchronous serial timing specifications changed in table. 11. a/d sample and conversion times example added. 12. note 1 of the 8-bit mode a/d characteristics table changed to state 20 mv, instead of 5 mv. this is the -001 version of the datasheet. the following changes were made in this version: 1. package thermal characteristics changed. table 17. thermal characteristics package type q ja q jc 160-pin qfp 34 c/w 5 c/w

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